Parallel and reconfigurable computing
Research towards solving fundamental problems and developing new applications for multi-core processors.
Parallel computing is more important than ever, given the mainstream move towards multi-core processors. Our research group investigates the various aspects of parallel and reconfigurable computing rangingf from fundamental problems like task scheduling, to the development of visual tools.
A strong focus is on the exploitation of new forms of parallelism, be it the use of reconfigurable hardware for high performance computing or the parallelisation of (object oriented) desktop applications.
Parallel computing has existed for many decades, though it remains a challenging field with many unresolved problems. The physical limits of processor technology and the shift towards multi-core systems makes this area more relevant and important than ever. Our research includes – but is not limited to – the following topics:
Modern computer systems have more than one processor-core. To benefit from this processing power, we need to parallelise our programs. For desktop applications such as browsers and word processors, this mainly requires object oriented (OO) applications to be parallelised. We investigate novel methods and techniques for the parallelisation of such programs without jeopardising the benefits of high-level OO languages.
Crucial to the efficiency of a parallel program is how the (sub)tasks of said program are mapped and ordered on the system’s processors. In task scheduling, the program is represented by a graph, where its nodes represent the tasks and the edges of their communication. The objective is then to find the best scheduling of this graph on the processors that allows the fastest execution of the program. Unfortunately, this is a very difficult optimisation problem (NP-hard). We investigate realistic system models, novel approaches and algorithms for this problem to make scheduling more efficient and accurate.
A reconfigurable hardware system constructed from FPGAs can provide much higher performance for certain applications than general purpose parallel systems. The advantage comes from the potentially much higher concurrency of many small processing elements that can work in parallel. Unfortunately, configuring a reconfigurable system is even more challenging than programming a parallel system. We investigate how reconfigurable hardware can be integrated into general purpose parallel computing. We also develop tools based on high-level programming languages and investigate how reconfigurable systems can be used in certain areas, such as bioengineering.
Visualisation and development tools
Development tools are indispensable to the quick and efficient creation of programs. Strangely though, there are not many powerful tools available for parallel programming, even though it is more involved and complex than sequential programming. We investigate such tools, with a focus on visual aids. For example, we develop tools that can visualise the dependences between code parts or display the scheduling of the tasks on processors. The design aim includes a deep integration with the existing development process. We are currently undertaking this research in the Parallel and Reconfigurable Computing Lab with our several parallel and reconfigurable computing systems.
Square Kilometre Array (SKA)
The Square Kilometre Array (SKA) will soon be the world's largest radio telescope array and is currently in its (pre-)construction phase. With 11 member countries involved at its current stage, it is a mega-science project with a projected budget of more than half a billion Euros. Upon its completion, it will help radio astronomers and scientists to investigate the major open questions in science such as strong field physics, probing the Cosmic Dawn, and the Cradle of Life.
Large antenna arrays will be built on selected sites in South Africa and Australia, though one of the SKA’s biggest challenges would remain its unprecedented processing and data communication requirements. Gigantic streams of data signals will need to be processed in real time, with a rate that will exceed the culmination of global internet traffic in recent years, thus posing major engineering challenges.
The SKA’s construction and design is largely a High Performance Computing and Data Science project that is reflective of the challenges we will see in future supercomputers and big data projects. We are currently investigating and designing high performance solutions for radio astronomical algorithms and methods – mostly based on FPGAs – programmed with high level approaches.